1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
Recently, with the high integration of semiconductor devices, MOSFETs (Metal oxide Semiconductor Field Effect Transistors) constituting a semiconductor device also have been miniaturized. This miniaturization reduces width of the wirings and also reduces depths of source/drain diffusion layers, thereby increasing electric resistances of the wirings and the diffusion layers etc., which increases a delay of signal transmission. In order to prevent such electric resistances from increasing, it is required for an impurity concentration distribution curve in a high concentration diffusion region to represent steep inclines with respect to both a longitudinal direction and a lateral direction. Further, there is employed a method of forming a low resistance silicide on a gate electrode or a diffusion layer in a self-aligning manner.
In an nMOSFET (n-channel Metal oxide Semiconductor Field Effect Transistors), high concentration diffusion region having an impurity concentration distribution curve representing steep inclines is attained by employing arsenic as impurity. However, when forming silicide, there are some problems. That is, it is reported that forming silicide on a silicon substrate highly doped with an impurity, in particular, arsenic, allows an irregular silicide layer to form. Refer to, for example, T. Ohguro, T. Morimoto, Y. Ushiku, and H. Iwai “Analysis of Anomalously Large Junction Leakage Current of Nickel Silicided N-Type Diffused Layer and Its Improvement” Extended Abstract of the 1993 International Conference on Solid State Devices and Materials, 1993, pp. 192-194.
For example, when employing arsenic as an impurity to be doped and forming a nickel silicide layer as a silicide layer to be formed, nickel is deposited on a silicon substrate containing arsenic, followed by siliciding the deposited nickel by the use of heat treatment. In this case, however, the silicide layer formed on the silicon substrate unfavorably becomes an irregular silicide layer composed of not only nickel silicide, but also a compound containing nickel, silicon, oxygen, and arsenic.
In a conventional CMOS process, there is simultaneously carried out an impurity doping into a semiconductor substrate for forming a highly doped diffusion layer and an impurity doping into the gate electrode. For this reason, arsenic is doped into the gate electrode by the same amount as that into the highly doped diffusion layer. Therefore, forming a nickel silicide layer on the gate electrode causes an irregular silicide layer to be unfavorably formed. This silicidation may not only cause the silicide layer on the gate electrode to be formed thicker than the silicide layer on the silicon substrate, but also cause the entire of the gate electrode to be silicided. Carrying out the doping into the gate electrode in synchronization with the doping into the semiconductor substrate for forming the highly doped diffusion layer provides a problem that the gate electrode is not subjected to ion-implantation at the most suitable concentration.
Excessively siliciding the gate electrode causes the sheet resistance of the silicide layer to be varied. Further, this excessive silicidation of the gate electrode may reach the entire of the gate electrode, thereby causing the silicided gate electrode to contact the gate insulating film to thereby change the work function of the gate electrode, which causes the threshold voltage to be unfavorably shifted or varied. This remarkably reduces the reliability of the semiconductor device.